SoC Architect

It is designed to provide end-to-end mastery of modern System-on-Chip architecture, enabling learners to understand, design, model, and analyze the full range of subsystems that make up today’s high-performance SoCs.

The program covers all major architectural domains, including CPU, GPU, DSP, ISP, NPU, memory hierarchy, interconnects, power domains, clock/reset/boot flows, and security architecture. Through in-depth theory and practical modeling exercises, learners explore:

– AMBA protocols and NoC fabrics
– Cache and memory subsystem design
– IP integration and SoC assembly
– DVFS-based power management and multi-voltage planning
– Security frameworks such as TrustZone, secure boot, and crypto engines
– Performance, bandwidth, and latency modeling
– SystemC/TLM design for architectural simulation
– Verification and validation of SoC-level architecture

Hands-on projects include bandwidth and power modeling, TLM subsystem simulation, power-domain planning, and interconnect design, allowing learners to apply real-world architectural thinking. The course culminates in a high-end capstone project such as a RISC-V quad-core SoC, AI accelerator SoC, automotive SoC, or edge-compute SoC, built at an architectural level.

By the end of the program, participants are prepared to:

– architect and model complex SoC platforms,
– perform system-level performance and power analysis, and
– take on senior roles in SoC architecture, system design, and semiconductor R&D.

This course provides essential knowledge and practical training to build industry-relevant skills.

Fees: ₹3500, ₹2000 (incl. GST) (Excluding tools & equipment cost)

Certification: TCoE

Duration: 72 Hours (2 hours/day x 6 days/week x 6 weeks) OR at your own pace